1. Field of the Invention
The present invention relates to semiconductor circuit structures, and in particular, to semiconductor circuit structures providing electrostatic discharge (ESD) protection for integrated circuits.
2. Description of the Related Art
Electrostatic discharge (ESD) protection devices are widely used in an integrated circuit (IC) to protect the electronic devices within the IC, e.g., bipolar junction transistors (BJTs) and metal oxide semiconductor field effect transistors (MOSFETs), from spurious voltage pulses caused by various sources of electrostatic energy. Numerous conventional ESD protection structures and devices are well known in the art, and include the use of BJTs, MOSFETs, grounded gate metal oxide semiconductor (GGMOS) structures, low voltage triggered silicon controlled rectifiers (LVTSCRs), triacs and diacs.
Electrostatic discharge events produce voltages that typically have large magnitudes and can be either positive or negative in polarity (i.e., with respect to the reference, or ground, potential of the circuit to be protected). Most conventional ESD protection structures can only protect against ESD events of a single polarity. Accordingly, for protection against both positive and negative ESD voltages, at least two distinct ESD protection structures are normally required.
For some applications, as a practical matter, only one dedicated ESD protection structure need be provided for protecting against positive ESD event voltages. Negative ESD event voltages can be clamped at a safe voltage by the inherent body diode present in most circuits (discussed in more detail below).
Referring to FIG. 1, one common device used for an ESD protection structure is a diac 10, which is well known in the art. Between the two electrical terminals 11a (T1), 11b (T2) multiple semiconductor layers 12p, 12n, 14, 16n, 16p. As is well known, the diac 10 is a bi-directional device that becomes conductive when the voltage at one terminal T1 (T2) becomes more positive than the voltage at the other terminal T2 (T1) by an amount greater than the predetermined trigger voltage, and remains conductive, i.e., continues to conduct current from the more positive to the less positive terminal, until such inter-terminal voltage becomes less than a predetermined holding voltage.
Referring to FIG. 2, the implementation of a diac 10a as an ESD protection structure within an IC environment typically appears as shown. The P-type substrate 14, which is typically connected to a circuit reference, or ground, electrode 18, has two N-type wells 12n, 16n diffused or implanted into its surface, separated by a gap region 14g. Within the first well 12n are a similarly diffused or implanted N-type contact region 12na and P-type contact region 12p both of which are connected to one of the diac terminals 11a. Within the second well 16n are another similarly diffused or implanted N-type contact region 16na and P-type contact region 16p, both of which are connected to the other diac terminal 11b. As noted above, this diac structure 10a will provide protection for a positive voltage appearing across the terminals 11a, 11b (one of which is typically connected to the circuit reference electrode 18), but will not provide the primary protection against negative ESD voltages due to the so-called “body diode” which exists by nature of the PN junction between the P-type substrate 14 and the N-type well 12n/16n. 
For many circuits or applications, such asymmetrical ESD protection can be acceptable. However, some circuits or systems must be tolerant of negative voltages appearing at the terminals to be protected from ESD events without being clamped at the typically low voltages associated with the body diode. One example of such a circuit would be a circuit used for measuring current in the operation of a circuit or system with a heavy inductive load (e.g., for driving a motor). For proper accuracy, influences created by the chip during operation of the host circuit or system must be minimized, including avoidance of premature voltage clamping caused by voltage spikes which may at first appear, albeit incorrectly, to be an ESD event.